1. Field of the Invention
This invention relates to a high switching speed transistor, and more particularly to a semiconductor device structure for bipolar transistors, field effect transistors, integrated injection logic circuits and the like.
2. Description of the Prior Art
A semiconductor device shown in sectional view in FIG. 1A is a conventional bipolar transistor which has been used in a semiconductor integrated circuit (IC, LSI).
In the conventional bipolar transistor, e.g. an NPN transistor, a base region 14 of p conductivity type formed in a Si epitaxially grown layer 13 of n conductivity type which is formed on a Si substrate 11 of p conductivity type and an n-type emitter region 15 is formed in the base region 14. In FIG. 1A, numerals 12 and 12' denote an n.sup.+ -type buried layer and an n.sup.+ -type contact region for a collector electrode, respectively, and numeral 16 denotes a p-type isolation region for isolating adjacent elements. In the structure of the prior art device, all regions are formed by pn junctions irrespective of active regions or non-active regions of the transistor. Accordingly, it has the following disadvantages;
(i) Since a capacitance between the non-active region in the base region and the collector region is large, power dissipation is high. This is disadvantageous for a high speed operation.
(ii) Since the base region 14, the emitter region 15, the n.sup.+ -type diffusion region 12' and the isolation region 16 are formed by photoetching processes separately, a designer must take margin for alignment of respective photomasks into consideration. This results in large gate areas.
The problem (i) discussed above is particularly serious.
Generally, switching speed and power dissipation which are basic factors to indicate the performance of the integrated circuit depend on a magnitude of current in the transistor included and an electrostatic capacitance of the elements, including parasitic elements, which are to be charged and discharged by that current. Since the electric power required to operate the transistor at a given magnitude of current is proportional to that capacitance value, it is preferable that the capacitance value is as small as possible. For a given sheet resistance, a time constant of the transistor is also proportional to the capacitance value. Accordingly, the reduction of the capacitance value must be considered to increase the switching speed of the transistor.
FIG. 1B shows a structure, in sectional view, of a prior art insulated-gate field effect transistor (MOS FET). In the conventiona n-channel MOS FET, n-type regions 102 and 103 which are to function as a source region and a drain region, respectively, are formed in a p-type substrate 101, and a gate electrode 104 is formed on a gate insulating film 105. Numeral 106 denotes selectively formed device isolating insulating films. In this device structure, source and drain electrodes S and D must be taken out through holes (contact holes) smaller than the source and drain regions 102 and 103, respectively. As a result, the souce and drain regions are to be at least larger than the contact holes and hence parasitic capacitances C.sub.DS and C.sub.SS between the source and drain regions and the substrate 101 are large enought to be innegligible. FIG. 1C shows an equivalent circuit for the MOS FET having the parasitic capacitances C.sub.DS and C.sub.SS. Since the switching speed of the MOS FET depends on charge-discharge time for the capacitance C.sub.DS and the gate capacitance of the succeeding stage MOS FET, a high speed operation is attainable by reducing the parasitic capacitance C.sub.DS.